This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
Various abbreviations that appear in the ensuing description and/or drawing figures are defined as follows:    eMMC embedded MultiMediaCard    JEDEC joint electronic device engineering council    SD secure digital (memory card)    SDA secure digital association    SRAM static random access memory    SSD solid state disk    UFS universal flash storage (JEDEC next generation mass memory definition post-eMMC)
Different types of flash-based managed mass storage memories currently exist. A basic premise of such mass storage memory is to hide the flash technology complexity from the host system. A technology such as eMMC is one non-limiting example.
FIG. 1A reproduces FIG. 2 from JEDEC Standard, Embedded MultiMediaCard (eMMC) Product Standard, High Capacity, JESD84-A42, June 2007, JEDEC Solid State Technology Association, and shows a functional block diagram of an eMMC. The JEDEC eMMC includes, in addition to the flash memory itself, an intelligent on-board controller that manages the MMC communication protocol. The controller also handles block-management functions such as logical block allocation and wear leveling. The interface includes a clock (CLK) input. Also included is a command (CMD), which is a bidirectional command channel used for device initialization and command transfers. Commands are sent from a bus master to the device, and responses are sent from the device to the host. Also included is a bidirectional data bus (DAT[7:0]). The DAT signals operate in push-pull mode. By default, after power-up or RESET, only DAT0 is used for data transfer. The memory controller can configure a wider data bus for data transfer using either DAT[3:0] (4 bit mode) or DAT[7:0] (8 bit mode).
One non-limiting example of a flash memory controller construction is described in “A NAND Flash Memory Controller for SD/MMC Flash Memory Card”, Chuan-Sheng Lin and Lan-Rong Dung, IEEE Transactions of Magnetics, Vol. 43, No. 2, February 2007, pp. 933-935 (hereafter referred to as Lin et al.). FIG. 1B herein reproduces Figure 1 of Lin et al., and shows an overall block diagram of the NAND flash controller architecture for a SD/MMC card. The particular controller illustrated happens to use a w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) designed to correct random bit errors of the flash memory, in conjunction with a code-banking mechanism. The controller contains various RAMs, e.g., buffer RAM, bank RAM and common RAM.
In a NAND-flash device, as opposed to a NOR-flash device where cells are connected in parallel, the individual cells are connected in series in a manner that resembles a NAND gate. The series connection prevents the cells from being programmed individually. The cells are read out in series.
The eMMC/SD/UFS type of so-called managed NAND devices include the controller that manages the flash (NAND) memory. Typically these devices (controllers) include some embedded SRAM to store device metadata such as a physical-logical address conversion table or a portion of the physical-logical address conversion table. To minimize the size of the conversion table a block mapping scheme can be used. While the use of a page mapping scheme could be more efficient for certain use cases, the size of the resulting physical-logical address conversion table would increase significantly. However, even with the use of block mapping the physical-logical address conversion table typically does not fit fully into the SRAM due to, for example, cost optimization considerations of the controller/device. The resulting requirement to transfer, during use, portions of the physical-logical address conversion table to and from the flash memory results in slower device operation.
A portion of the physical-logical address conversion table can be loaded based on address information in a received memory access command. For example, reference can be made to Tae-Sun Chung, Hyung-Seok Park, “STAFF: A flash driver algorithm minimizing block erasures”, Journal of Systems Architecture: the EUROMICRO Journal, Vol. 53, Issue 12 (December 2007), pp. 889-901.
In high end applications (such as portable computer applications) there are typically sufficient resources and memory so that the entire physical-logical address conversion table can be accommodated.
Lee et al. in US 2008/0195802 A1, “System and Method for Searching Mapping Table of Flash Memory”, describe the use of two random access memories, specifically a fast SRAM and a slower DRAM, for storing the flash mapping table. In FIG. 7 of Lee et al. there is shown an example of dividing and loading mapping table data according to importance, size, and search frequency. In this approach first mapping table data, e.g., page mapping table data, having a higher importance, smaller size, or higher search frequency among the entire mapping table data is loaded into the SRAM, while second mapping table data, e.g., bad-block mapping table data and logical-to-physical mapping table data, having lower importance, larger size, or lower search frequency is loaded into the slower DRAM.
One clear disadvantage of this approach is that two memories are needed in the flash controller for storing the mapping table data.